July 2, 2009
Pulsic Limited has been granted US Patent #11383658 for a unique routing innovation incorporated in their physical chip design software. The patent, titled Automatic routing nets according to current density rules, protects unique technology incorporated in Pulsic’s UniRoute automated router. By taking into account the current required by the individual branches in a net, UniRoute is able to optimize a net’s width. This innovation creates the smallest net width that satisfies the electro-migration rules for current density. Optimizing the net widths not only eliminates the risk of electro-migration, but also significantly reduces IR losses and minimizes routing area. For layout engineers, this eliminates the need to estimate current densities and manually calculate varying net-widths for high fan-out interconnects.
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS 
No Comments »
July 1, 2009
IntervalZero and Adeneo Embedded have teamed together to create Soft-Control Accelerator. The joint product offering helps Embedded OEMs migrate to a Soft-Control Architecture. Soft-Control Accelerator features an IntervalZero RTX 2009 SMP software development kit with a year of support and a three-day, on-site Adeneo services engagement that can be customized to meet the OEMs’ needs. Soft Control Accelerator will be offered in North America and is available only from Adeneo Embedded.
Read more: Soft Control Accelerator for Soft Control Architecture
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 30, 2009
Semiconductor Manufacturing International Corporation (SMIC) has successfully completed their first 45-nanometer high performance (GP, generic process with high performance) yield lot. The high-speed, high performance 45nm GP technology integrates a silicon germanium stress module into the design. The process enables the device to run faster and make it ideal for system-on-chip, graphics and network processors, telecommunications, and wireless consumer products. SMIC’s 45nm GP technology is supported by a proven design-in SPICE model and in-house design IP capability that enables customers to begin prototype product design and plan for early time-to-market.
More info: SMIC
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 29, 2009
Forte Design Systems rolled out the version 3.6 of Cynthesizer SystemC synthesis software for hardware and electronic system level (ESL) design. The new Cynthesizer features SystemC 2.2 support, tools for partitioning complex hierarchical systems, automated generation of complex interfaces, enhanced control-based design support, memory support upgrades, and scalability improvements. Cynthesizer comes standard with Forte’s transaction level modeling (TLM) synthesis capability. U.S. pricing starts at $275,000. Cynthesizer’s Partitioning and Interface Generator features start at $40,000 (U.S.) as an add-on to Cynthesizer to further improve productivity.
Read more: Forte Design Systems Cynthesizer 3.6 SystemC Synthesis
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 29, 2009
The Catapult C Synthesis 2009a release, from Mentor Graphics, features support for control logic and manage low power design requirements, thus enabling full-chip high-level synthesis (HLS). The enhancement enables designers to use pure ANSI C++ for both algorithmic blocks and control logic blocks. The Catapult C Synthesis tool automatically generates control and algorithmic RTL multi-block designs from a pure ANSI C++ source where both the core algorithm and interface are untimed. The Catapult C Synthesis 2009a release is available to customers in July. The Catapult C product family ranges from $140,000 to $390,000.
Read more: Mentor Graphics Catapult C Synthesis 2009a Release
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 29, 2009
The OPC Training Institute will develop customized OPC training for Honeywell based on Experion PKS. The course is ideal for Honeywell engineers, end-users, EPC contractors, and system integrators. The class will equip attendees with an understanding of OPC technology and planning, designing and implementing secure and reliable OPC interface to Experion PKS Systems. The training will be held at Honeywell’s Automation College locations globally. OPC is a global industrial connectivity standard that enables process control and manufacturing applications to communicate with each other using an interoperable, reliable, and secure connection.
More info: OPC Training Institute
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 26, 2009
Technical and manufacturing experts from SEMATECH and International SEMATECH Manufacturing Initiative (ISMI) will offer a series of lectures and workshop sessions from July 14-16, 2009 at SEMICON West in San Francisco. The lineup features five expert speakers representing SEMATECH and its subsidiary ISMI, who will appear on the Device Scaling TechXPOT Stage in the North Hall of Moscone Center. Topics will include CMOS scaling, 3D interconnects, extreme ultraviolet lithography, and ESH challenges.
Read more: SEMICON West 2009 Speakers and Workshops
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 26, 2009
The 2009 Asia Symposium on Quality Electronic Design (ASQED09) will take place July 15-16, 2009 in Kuala Lumpur, Malaysia. The program consists of keynote speeches from Synopsys, NXP, Cadence Design Systems, University of Tokyo, and Verdant Electronics. The event also features tutorials, panel discussion, and over 80 technical presentations. Techanical papers will be presented in three parallel tracks on Wednesday July 15th and Thursday July 16th.
Read more: 2009 Asia Symposium on Quality Electronic Design
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 25, 2009
The Sonics MemMax DRAM System is a pre-configured, verified, and silicon-proven IP block that can be integrated into a variety of SoCs quickly and easily. The IP block is a combination of Sonics’ advanced memory scheduler and Synopsys’ DesignWare DDR Protocol Controller IP. The combination results in an IP block that is optimized for maximum DRAM access efficiency and scalability as designs move from DDR2 to DDR3. Based on Sonics’ proprietary scheduling technology, designers can experience up to 85% memory bandwidth utilization from the system through to the external DRAM memory. The MemMax DRAM System is available now from Sonics.
Read more: Sonics MemMax DRAM System
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
June 25, 2009
LDRA has integrated their tool suite with the Analog Devices VisualDSP++ (VDSP++) software development environment. VDSP++ creates a software development environment for engineers working with Analog’s embedded processors. The LDRA tool suite offers automated software testing and verification across all stages of software development. The integration enables seamless testing of user code at both the unit and system levels, coupled with enhanced error detection to speed up the overall software development process.
Read more: LDRA Tool Suite Integrates with the Analog Devices VisualDSP++
Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek
© 2009 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd
Originally posted here.
Posted in RSS No Comments »
Online since 1994.
